operating-system-mmu.html


* created: 2025-05-28T18:38
* modified: 2025-07-03T08:52

title

Memory management unit

description

The memory management unit or mmu is responsible for translating logical addresses into physical ones.

related notes

Translating digital to physical addresses

The memory management unit is responsible for translating logical addresses into their physical counterparts; physical means the address under which the data can be found inside our main memory.

This translation has to happen quite fast, since need to calculate each individual physical address if we wanted to access something in memory.

To illustrate how many times this happens we could look at the execution of a simple instruction:

So we can assume that the MMU has to calculate the physical address 2-4 times during a single instruction cycle.

Page tables

To achieve this the MMU uses a page table, which is a data structure that maps logical page numbers to physical frames. Each individual process has its own page table, which is stored somewhere in the physical memory. To know where to find these individual page tables, the MMU keeps track of them using a page table register.

Each process has its own page table!

Structure

address present/absent Bit M-Bit R-Bit
0 0000 0010 0101 1 0 1

Example

To showcase how the translation happens we need to look at some numbers first.

Physical Memory: 512 MiB Logical Memory: 4 GiB Page Frame: 64 KiB

The Physical Memory would consist of 2^{29} Byte and \frac{512 MiB}{64 KiB} = 2^{13} page frames. The Logical Memory would consist of 2^{32} Byte and \frac{4 GiB}{64 KiB} = 2^{16} pages. Each Page Frame would consist of 2^{16} Byte.

We can now assert that our logical address would have to be at least 32 Bit long. These 32 Bit consist of 16 Bit for our pages and 16 Bit for our logical memory cell inside this page.

The physical address consists of 29 Bit. 13 Bit for the page frame and again 16 Bit for the memory cell inside the page frame.

The mmu has to calculate a 29 Bit physical address out of a 32 Bit logical address. To this a page table is being used. The page table consists of 2^{16} rows; each row representing one of 2^{16} pages. The corresponding row gets addressed using the first 16 Bit of our logical address. Inside the row we find a present/absent Bit.

If the required data is currently in memory — indicated by the present/absent bit being 1 — then a 13-bit value in the corresponding row specifies the page frame where the page is stored.

The only thing the MMU has to now is replacing the first 16 Bit (which are being used to address the corresponding row inside the page table) with the 13 Bit stored inside the row to get our physical address.