Von Neumann Architecture

The represents a general reference system for a computer which consists of 4 main components: CPU, I/O-Unit, Memory-Unit and a central Bus-System.

Each component can be broken down in a complex sub-structures which intern have their own sub-modules.

General structure:

• Arithmetic Logic Unit: Executes basic arithmetic logic on values currently present in the input register and writes result into accumulator.
• Memory Address Register: Holds addresses for data or instructions.
• Memory Data Register: Holds data that is being transferred from ant to memory.
• Control Unit: Manages the fetching, decoding and execution of instructions and the general data flow.

BUS (Binary Unit System)

Link: Bus

Von Neumann bottleneck

The Central Processing Unit and Memory are separat and need to communicate over a shared bus. Both instructions and data reside in the same memory; since they are fetched over the same bus system the CPU can only fetch one at a time.

This is mitigated through separat instruction and data memory and bus system in the Harvard-Architecture.

Von Neumann Cycle

1. Fetch: Fetch the instruction which address is currently stored in the program counter.
2. Decode: Decode that instruction.
3. Load: Load the operands necessary for the execution of said instruction.
4. Execute: Execute said instruction.
5. Write: If necessary write the resulting value back.