No RISC no fun

The RISC (Reduced Instruction Set Computer) architecture was developed in the early 80s utilizing the upcoming technology of encoding machine instruction through a single micro instruction which are executed directly on the chip.

This came with limitation of greatly reducing the instruction set in comparison to CISC.

What is Pipelining?

Pipelining describes the process of executing the phases of an instruction cycle (fetch, decode, load, execute and write) in parallel with an offset. This happens during the execution of processes on a RISC architecture.

You could look at the following example; let's take two instruction:

ADD A, B
ADD C, D

If we plotted the execution cycle on a table, it would look something like this:

F: fetch D: decode L: load E: execute W: write